library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity invertBitGenerator is
port(
  A 	: in std_logic_vector(31 downto 0);
  B 	: in std_logic_vector(31 downto 0);
  inv 	: out std_logic
);
end invertBitGenerator;

architecture rtl of invertBitGenerator is
signal u,level0,level1,level2,level3,level4: unsigned(31 downto 0);
signal hamming : unsigned (5 downto 0);
constant mask0 : unsigned(31 downto 0) := "01010101010101010101010101010101";
constant mask1 : unsigned(31 downto 0) := "00110011001100110011001100110011";
constant mask2 : unsigned(31 downto 0) := "00001111000011110000111100001111";
constant mask3 : unsigned(31 downto 0) := "00000000111111110000000011111111";
constant mask4 : unsigned(31 downto 0) := "00000000000000000000000011111111";
begin
	u		<= unsigned(A xor B);
	level0 	<= (u and mask0) + (('0' & u(31 downto 1)) and mask0);
	level1 	<= (level0 and mask1) + (("00" & level0(31 downto 2)) and mask1);
	level2 	<= (level1 and mask2) + (("0000" & level1(31 downto 4)) and mask2);
	level3 	<= (level2 and mask3) + (("00000000" & level2(31 downto 8)) and mask3);
	level4 	<= (level3 and mask4) + (("0000000000000000" & level3(31 downto 16)) and mask4);
	hamming <= level4(5 downto 0);
	inv 	<= '0' when (hamming < 16) else '1';
end architecture rtl;
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity busInvertCoder is
port(
  clk	: in std_logic;
  reset	: in std_logic;
  A 	: in std_logic_vector(31 downto 0);
  B 	: out std_logic_vector(32 downto 0)
);
end busInvertCoder;

architecture rtl of busInvertCoder is
component invertBitGenerator is
port(
  A 	: in std_logic_vector(31 downto 0);
  B 	: in std_logic_vector(31 downto 0);
  inv 	: out std_logic
);
end component;
signal inv : std_logic;
signal lastB : std_logic_vector(31 downto 0);
signal nextB : std_logic_vector(32 downto 0);
begin
	invBit :invertBitGenerator port map(A,lastB,inv);
	nextB <= inv & (A xor (31 downto 0 => inv));
	seqBlock : process (clk) is
	begin
		if reset = '1' then
			lastB <= (31 downto 0 => '0');
		elsif rising_edge(clk) then
			lastB 	<= nextB(31 downto 0);
			B 		<= nextB;
		end if;
	end process seqBlock;
end architecture rtl;
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity busInvertDecoder is
port(
  clk	: in std_logic;
  B 	: in std_logic_vector(32 downto 0);
  A 	: out std_logic_vector(31 downto 0)
);
end busInvertDecoder;

architecture rtl of busInvertDecoder is
signal nextA : std_logic_vector(31 downto 0);
begin
	nextA <= B(31 downto 0) xor (31 downto 0 =>B(32));
	seqBlock : process (clk) is
	begin
		if rising_edge(clk) then
			A <= nextA;
		end if;
	end process seqBlock;
end architecture rtl;